1. Field of the Invention
This invention relates to data processing systems, and more specifically to improved mechanisms for controlling the access of data from page mode addressed dynamic random access modules (DRAMS). These DRAMs are memories organized into rows and columns for page mode access of the memories as sets, banks or modules.
2. Description of Prior Art
FIG. 1 except for dashed line 103 shows a prior art processing system whereby dynamic random access memories in each of the modules are accessed via page mode to obtain a line of data. The system includes one or more independent central processors (CP) 11a through 11n, a system interconnection network (SC) 12 containing one or more memory controllers (MC) 13a through 13i, and one or more memories 14a through 14i. Each memory contains an address latch with incrementer 15, one or more banks of DRAMs 16, a speed matching fetch data buffer 17, and a data transfer selector 18. The memory logic which interfaces directly with the DRAMs, i.e. everything within the memory 14 with the exception of the DRAMs 16, is termed the memory support circuitry.
A cache within each CP holds lines of data which it has most recently used. When a word of data required by a processor is not found in its cache the CP requests this data from the SC. The SC obtains the most recent copy of the line containing this word (whether it is in memory or in another processor's cache) and transfers it to the requesting CP. In the cycles which immediately follow the transfer of the requested word the SC transfers the remaining words which comprise the line.
DRAMs are accessed via page mode to obtain a line of data in prior art memory designs. Page mode is a mode by which a single row address and a plurality of column addresses access a plurality of data bits from each DRAM data I/0 (input/output). In such designs only a portion of a data line is accessed with each column address. The benefits of such designs have been well documented. When page mode is invoked to access a line of data less DRAMs are activated and therefore less power is consumed on a line access. Also page mode reduces the data I/0 requirements between the DRAMs and speed matching buffer. The reduced 1/0 requirements allow for improved memory integration (memory designs with fewer cards) or increased data line sizes.
Unfortunately page mode designs have disadvantages also. One, the memory cycle time is increased because each memory access requires multiple column addresses and multiple column address strobe pulses. Also memory line data is loaded piecemeal into the speed matching fetch buffer. Generally the word required by the processor is the first to be loaded into the fetch buffer. However, the next sequential words within the line are not always available to be transferred in subsequent cycles. The subject invention addresses this problem.